With the complexity of silicon designs growing and the shift to multi-chip integration, challenges in performing post silicon debug increase. For example, system-on-chip (SoC) implementations are becoming more prevalent in many different product lines. As customers expect smaller form factors, the difficulty of debugging such system increases. This is especially so, as interconnects between components on a single silicon die are hidden from capture by an external logic analyzer.
In addition to the rising number of transistors on the silicon, the cost of using external logic analyzers to capture high frequency signals at speed is also growing. Often design teams embed debug hooks in the circuitry. However, due to the sensitive nature of internal nodes and software tools associated with their viewing, these powerful debug features are generally not available to customers. This forces any customer issues to be reproduced in a vendor site lab (versus at the customer site). It can be very difficult to reproduce these issues outside of the customer site.